1. Field of the Invention
The present invention relates to a protection circuit for a semiconductor integrated circuit and a driving method therefore, and in particular, to a protection circuit that protects a semiconductor integrated circuit or a system comprising a plurality of semiconductor integrated circuits against a surge, and a driving method for the protection circuit.
2. Description of the Related Art
Environmental problem is concerned in a various field of technology these days, and a reduction of CO2 is required for example. In such circumstances, a technique is required to reduce as much power consumption as possible in electric and electronic devices. Recent electric and electronic devices comprises a plurality of semiconductor integrated circuits (referred to as IC hereinafter), and for the above purpose to reduce power consumption, a technique in which a voltage source is not applied to an IC which is not used is employed. In many applications, a controlling IC which controls the system is kept at an operating state, whereas another IC is supplied with voltage source only when needed. Supposing that the controlling IC is IC2, the another IC is IC1.
Conventionally known protection circuits for semiconductor integrated circuits include, for example, one utilizing a PN junction diode as disclosed in Japanese Patent Application Laid-Open No. H05-021714 and one utilizing the snapback characteristics of MOSFETs as disclosed in Japanese Patent Application Laid-Open No. 2000-058666.
FIG. 7 illustrates conventional system connections used to apply different power source voltages to two ICs, IC1 and IC2. FIG. 7 illustrates an example in which a PN junction diode is used as a protection circuit.
When power sources for IC1 and IC2 are controlled by respective systems, rise timings for the power source voltages of the respective systems may fail to coincide with each other. Then, one of the power source voltages may rise earlier. In this case, for example, a power source voltage Vcc1 for IC1 is not applied and is at a ground potential (GND). A power source voltage Vcc2 for IC2 has already been applied. Thus, a buffer output from IC2 is at a high level, that is, IC2 outputs the power source voltage Vcc2. At this time, the power source voltage Vcc2 is applied to a protection diode D1 for IC1. That is, a voltage of at least several V is applied to the protection diode D1 in a forward direction. Thus, a current of several amperes may flow through the protection diode D1 to thermally break down the protection diode D1. When the protection diode D1 is broken down, the system may fail to operate.
FIG. 8 illustrates an example of system connections in which a MOSFET is used as a protection circuit for IC1. Also in this case, a similar phenomenon may occur because of a parasitic PN diode D1 present between a back gate and a drain of the protection PMOSFET. Moreover, the flow of the large current may cause a PNPN structure present in a CMOS process to be latched up.
To prevent an excessive current from flowing through the protection element and to prevent the possible latch-up, the following measures are conventionally taken.
(1) A power source sequence applied to each IC is controlled.
(2) A series resistor is placed in a terminal to which a voltage equal to or higher than the power source voltage may be applied.
However, disadvantageously, the measure in (1) increases system costs, and the measure in (2) cannot be used for a high-speed interface.